This invention relates to a method of recovering timing signals over asynchronous data networks, such as ATM networks (Asynchronous Transfer Mode), and especially for use with a synchronous TDM backplane, such as a Serial-Telecom bus (ST-BUS).
Asynchronous data networks are capable of offering constant bit rate services (CBR) for carrying time sensitive data, such as video and voice. For this purpose, clock signals must be recovered from the asynchronous network in order to ensure proper timing of the received signals. For example, in the case of PBX with an ST-bus trunked over an asynchronous network with a remote PBX also having an ST-bus, the ST-buses of the two PBXs must be synchronized with one the master and the other the slave.
The ITU (International telecommunications Union) has defined two ways of transporting timing across ATM networks: SRTS (Synchronous Residual Timestamp) and Adaptive method. Both are documented in the I.363 specification available from the ITU, the contents of which are herein incorporated by reference.
To guard against the loss of timing signals, it is generally desirable to have two sources of timing signal in the asynchronous network so that in the event of failure of one source, the system can switch to the other. Such switching usually results in a phase jump, which can momentarily interrupt a telephone conversation, and in the case of a data transmission, for example, fax transmission, result in data loss.
This problem is particularly acute in the case of simultaneous networking of multiple 64 kbps channels available on a Mitel ST-BUS backplane across an asynchronous data network, such as ATM. The Mitel ST-BUS backplane is a multi-serial stream bus whereby a plurality of 64 kbps TDM channels are transported with reference to an 8 kHz reference signal (F0) and CKx2 and CKx1 clocks respectively.
In the ST-BUS interface, channel zero on all the serial streams is aligned with the F0 synchronization pulse. Three different data rates are provided in the ST-BUS. These are 2.048, 4.096 and 8.192 Mbps rates. For all the three rate modes, CKx1 signal carries the bit rate of the specified mode and CKx2 carries twice as the data rate. As an example, if the ST-BUS backplane is operated at 8.192 Mbps, then CKx2 signal is at 16.384 MHz. The term common bit clock refers to signal CKx1.
In the case of the simultaneous transport of ST-BUS channels across an ATM network, the precise and continuous generation of timing signals is especially important to ensure quality of transmission and avoid loss of data. To achieve the function required, the source 2.048 MHz clock from the ST-BUS backplane has to be recovered at the other end with the same precision as the source.
An object of the invention is to meet this objective.
According to the present invention there is provided a method of generating timing signals for constant bit rate data received over an asynchronous data network, comprising the steps of recovering clock signals from at least two separate sources; selecting one of said sources to drive a phase-locked loop generating a high speed output signal locked to said selected source; dividing said high speed output signal to provide the required timing signals for said constant bit rate data; continually monitoring said selected source and in the event of failure thereof, switching over to said other source while allowing said phase-locked loop to free run in a hold-over mode during the switch over from one said source to the other.
In the "hold-over" mode, the phase-locked loop tracks an internal oscillator to maintain the output in synchronization with the reference signal as it was immediately prior to loss of synchronization until a new reference signal becomes avaiable.
The phase-locked loop runs at a frequency which is a multiple of the actual timing signals. For example, the PLL may generate a stable signal at 16 Mhz, which is divided by, 4, 8, and 2048 to derive CLKx2 (4 MHz), CLKx1 (2 MHz) and the ST-bus F0 (8 KHz) respectively.
The invention allows the user to recover a common bit clock from the asynchronous network, which drives all the serial streams of an ST-BUS synchronous interface from a primary or secondary reference, each associated with a separate ATM Virtual Circuit. If the primary source of clock fails, the invention ensures a hitless clock switch-over to the secondary reference.
This invention thus provides the emulation of any 64 or N.times.64 kbps channels or circuit across an ATM network. The N.times.64 kbps channels can be located anywhere over the multiple ST-BUS lines, forming a "groomed" channel. For the transmission and recovery of the ST-BUS common bit clock (CKx1) at the remote station, either ATM AAL 1 Adaptive or Sychronous Residual Time Stamp (SRTS) methods suggested by the ITU (I.363 is recommended) can be used.
By using the described hitless clock switch-over mechanism, the user can dynamically program or change the clock recovery mechanism from Adaptive to SRTS and vice-versa, on a per ATM VC (Virtual Circuit) basis.
An important advantage of the invention is that, at the receive end, once the common bit clock is recovered, the 64 or n.times.64 kbps channels are emulated and placed over an ST-BUS backplane with its integrity protected. The ST-bus F0 (8 KHz) reference phase does not change during clock switch over.
The invention allows the use of off-the shelf PLLs (Phase-Locked Loops) and digital logic to regenerate the ST-BUS CKx1 clock without incurring phase jumps. The TDM clock logic also allows the user to manually change from one time reference to another without corrupting the ST-BUS clock (i.e. hitless operation).
The invention thus permits channelized N.times.64 ST-BUS trunking over an ATM network by emulating the ST-BUS 2.048 MHz basic clock (derived from CKx2 input) from source to destination. The recovered common bit clock can be derived from a Primary or Secondary reference. Each reference has a separate ATM Virtual Circuit. If the Primary source of clock fails, the invention provides a hitless clock switch over to the secondary reference.
The 8 KHz reference (REF8KCK) clock is sourced either from a Primary recovered ATM VC clock or from a Secondary one. A monitor circuit is used to check the validity of the incoming SRTS or a timing cell in the case of an adaptive scheme within these VCs. Upon the detection of the synchronization failure or loss of synchronization, the circuit would switch the references. When a failure is detected on the incoming VC source, the external PLL is automatically forced to free run in the hold-ver mode. In this mode the PLL keeps its output frequency fixed and no further corrections are made.
The invention also provides a timing signal generator for use with over an asynchronous data network carrying constant bit rate data, comprising means for recovering clock signals from at least two separate sources over the asynchronous network; a phase-locked loop generating a high speed output signal; means for dividing said high speed output signal to provide the required timing signals for said constant bit rate data; means for selectively connecting either of said sources to said phase-locked loop so that the timing signals recovered therefrom drive said phase-locked loop; and means for continually monitoring one said source connected to said phase-locked loop, said monitoring means connecting the other source to the phase-locked loop in the event of failure of said one source, and said monitoring means further outputting a signal to cause said phase-locked loop to free run in a hold-over mode during the switch-over from one said source to the other.